1. Field of the Invention
The present invention relates to a class AB amplifier and, more particularly, to a CMOS amplifier useful in a variety of products such as operational amplifiers, chopper stabilized amplifiers, commutating autozero, amplifiers and the like.
2. Description of the Prior Art
FIG. 1 shows an amplifier circuit that is widely used in a variety of products. The amplifier is most conveniently implemented using complementary MOS technology and has been incorporated in operational amplifiers, chopper stabilized amplifiers, commutating autozero amplifiers and the like.
Such prior art amplifier circuit, generally designated 10, has an input terminal 11, an output terminal 12, a first voltage supply V+, a second voltage supply V-, four matched transistors having a given polarity, designated P.sub.1, P.sub.2, P.sub.3 and P.sub.4, two matched transistors having an opposite polarity, designated N.sub.1 and N.sub.2, a current source 13, a resistor R and a capacitor C.sub.1, all interconnected as shown. While amplifier 10 could be implemented with bipolar transistors, the preferred implementation utilizes CMOS technology so that transistors P.sub.1 -P.sub.4 are P-type transistors and transistors N.sub.1 and N.sub.2 are N-type transistors, although the types could be reversed. Each transistor has a pair of output terminals (source and drain), a control terminal (gate) and a substrate, the sources of all transistors being connected to the substrates, as shown. During the description of amplifier 10, reference will be made to the voltage at a node A, which is the common connection point of the drains of transistors P.sub.1 and P.sub.2 and the gates of transistors P.sub.2 and P.sub.3, and the voltage at a node B at the junction between the drains of transistors P.sub.3 and N.sub.1.
When implemented using CMOS technology, each transistor has a size which is defined as the ratio of the channel width W to the channel length L (W/L). In a typical implementation of amplifier 10, the sizes of the various transistors are adjusted relative to each other in accordance with the following relationships: EQU P.sub.1 /P.sub.2 =3, (1) EQU P.sub.4 /(P.sub.1 +P.sub.2)=N.sub.2 /N.sub.1 =25, and (2) EQU (P.sub.1 +P.sub.2)/P.sub.3 =1. (3)
While these values can be different, the above represents a preferred implementation of amplifier 10.
In discussing the operation of amplifier 10, certain assumptions will be made. That is, transistors P.sub.1 -P.sub.4 are matched in that they are all made from the same process steps and the threshold voltages of all are virtually identical. The same is the case with transistors N.sub.1 and N.sub.2. The quiescent operating point of amplifier 10 is defined when the voltage at node A equals the input voltage at terminal 11, V.sub.IN. The ratios of the transistor sizes are precisely as discussed above; the output impedances of all transistors are extremely high; and current source 13 is an ideal current source. The above assumptions are reasonable in that practical errors, such as transistor finite output resistances and mismatch of transistor sizes, will cause only minor errors, such as a slight difference in the voltage at node A as compared to the voltage at input terminal 11 for the setting up of the quiescent biasing conditions.
It should be noted that resistor R and capacitor C.sub.1 are usually required to provide the dominant pole and a zero when amplifier 10 is used in conjunction with a first stage (operational amplifier usage) to provide AC stablility. Under some circumstances, such as for low frequency operation or with loads that are not highly capacitive, R may be omitted. However, omitting R will degrade high frequency stability and performance.
An analysis of amplifier 10 will show that the value of the current I.sub.2 will equal the value of the current I.sub.1 and since transistor N.sub.2 will multiply the current I.sub.2 by the ratio of its size compared to N.sub.1, I.sub.3 will equal 25I.sub.1. The value of the current sourced by transistor P.sub.4 is identical to that sunk by transistor N.sub.2. The transconductance of amplifier 10 under quiescent conditions is four times the transconductance of transistor P.sub.4. Hence, in order to obtain a reasonably high ratio of maximum output sink current to quiescent current (here four), amplifier 10 has nonsymmetrical gain through its two signal paths to output terminal 12; one path going through transistors P.sub.1, P.sub.2, P.sub.3, N.sub.1 and N.sub.2 (hereinafter "the first signal path") and the other going through transistor P.sub.4 (hereinafter "the second signal path").
As the input voltage V.sub.IN is increased in a negative sense, the gain of the first signal path increases as the output sinking current through transistors N.sub.2 decreases. At the same time, the impedances at nodes A and B increase. The two poles associated with these two nodes decrease in frequency accordingly. These poles, together with the poles associated with the input and output nodes, can produce sufficient phase shift around the loop (from input node 11 to node A, to node B, to output node 12 back through R and C.sub.1 to input node 11) to cause instability at high frequencies. If the transconductance of transistor P.sub.4 could be increased, the overall loop gain could be increased. However, due to biasing considerations, P.sub.4 cannot be changed.
The conclusion is, therefore, that amplifier 10 has stability limitations which limit the gain through the first signal path so that the ratio P.sub.1 to P.sub.3 cannot be increased to a value greater than about three without limiting severely the capacitive loading on output node 12. On the other hand, it is desirable to be able to increase the ratio of P.sub.1 to P.sub.2 as high as possible to increase the ratio of peak sinking current in transistor N.sub.2 to the quiescent output current. A manner of doing this has been unknown heretofore.